| VLSI1 |
Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System |
Low power |
VHDL/2020 |
| VLSI2 |
RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory |
Low power |
VHDL/2020 |
| VLSI3 |
TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages |
Low power |
VHDL/2020 |
| VLSI4 |
A Compact 0.3-V Class AB Bulk-Driven OTA |
Low power |
VHDL/2020 |
| VLSI5 |
A Low-Power Reconfigurable Narrowband/Wideband LNA for Cognitive Radio-Wireless Sensor Network |
Low power |
VHDL/2020 |
| VLSI6 |
A Low-Power Reconfigurable Narrowband/Wideband LNA for Cognitive Radio-Wireless Sensor Network |
Low power |
VHDL/2020 |
| VLSI7 |
An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS |
Low power |
VHDL/2020 |
| VLSI8 |
Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks |
Low power |
VHDL/2020 |
| VLSI9 |
A Sub-1-V 100-mA OCL-LDO Regulator With Process-Temperature-Aware Design for Transient Sustainability |
Low power |
VHDL/2020 |
| VLSI10 |
A 600-mA, Fast-Transient Low-Dropout Regulator With Pseudo-ESR Technique in 0.18- μ m CMOS Process |
Low power |
VHDL/2020 |
| VLSI11 |
A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme |
Low power |
VHDL/2020 |
| VLSI12 |
Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield |
Low power |
VHDL/2020 |
| VLSI13 |
Gain-Cell Embedded DRAMs: Modeling and Design Space |
Low power |
VHDL/2020 |
| VLSI14 |
MERIT: Tensor Transform for Memory-Efficient Vision Processing on Parallel Architectures |
Low power |
VHDL/2020 |
| VLSI15 |
A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels |
Low power |
VHDL/2020 |
| VLSI16 |
A Low-Complexity Hybrid Readout Circuit for Lidar Receiver |
Low power |
VHDL/2020 |
| VLSI17 |
A New High Drive Class-AB FVF-Based Second Generation Voltage Conveyor |
Low power |
VHDL/2020 |
| VLSI18 |
Time-Domain Operational Amplifier With Voltage-Controlled Oscillator and Its Application to Active-RC Analog Filter |
Low power |
VHDL/2020 |
| VLSI19 |
A Low Phase Noise, High Phase Accuracy Quadrature LC-VCO With Dual-Tail Current Biasing to Insert Reconfigurable Phase Delay |
Low power |
VHDL/2020 |
| VLSI20 |
A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering |
Low power |
VHDL/2020 |
| VLSI21 |
All-Digital Cost-Efficient CMOS Digital-to-Time Converter Using Binary-Weighted Pulse Expansion |
Low power |
VHDL/2020 |
| VLSI22 |
Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications |
Low power |
VHDL/2020 |
| VLSI23 |
Optimizing FPGA Logic Circuitry for Variable Voltage Supplies |
Low power |
VHDL/2020 |
| VLSI24 |
A High-Performance LDO Regulator Enabling Low-Power SoC With Voltage Scaling Approaches |
Low power |
VHDL/2020 |
| VLSI25 |
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands |
Low power |
VHDL/2020 |
| VLSI26 |
One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation |
Low power |
VHDL/2020 |
| VLSI27 |
Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders |
Low power |
VHDL/2020 |
| VLSI28 |
High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell |
Low power |
VHDL/2020 |
| VLSI29 |
Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation |
Low power |
VHDL/2020 |
| VLSI30 |
Balanced (3 + 2 log n)G Adders for Moduli Set {2n+1 , 2n + 2n−1 − 1, 2n+1 − 1} |
Low power |
VHDL/2020 |
| VLSI31 |
Very Fast, High-Performance 5-2 and 7-2 Compressors in CMOS Process for Rapid Parallel Accumulations |
Low power |
VHDL/2020 |
| VLSI32 |
Error Probability Models for Voltage-Scaled Multiply-Accumulate Units |
Low power |
VHDL/2020 |
| VLSI33 |
A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage Operational Amplifiers |
Low power |
VHDL/2020 |
| VLSI34 |
Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO |
Low power |
VHDL/2020 |
| VLSI35 |
A 23–36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array in SiGe BiCMOS for 5G Applications |
Low power |
VHDL/2020 |
| VLSI36 |
A Discrete-Time MOS Parametric Amplifier-Based Chopped Signal Demodulator |
Low power |
VHDL/2020 |
| VLSI37 |
A Low-Latency and Low-Cost Montgomery Modular Multiplier Based on NLP Multiplication |
Low power |
VHDL/2020 |
| VLSI38 |
Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications |
Low power |
VHDL/2020 |
| VLSI39 |
Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process |
Low power |
VHDL/2020 |
| VLSI40 |
All-Digital CMOS Time-to-Digital Converter With Temperature-Measuring Capability |
Low power |
VHDL/2020 |
| VLSI41 |
An Analysis of DCM-Based True Random Number Generator |
Low power |
VHDL/2020 |
| VLSI42 |
A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits |
Low power |
VHDL/2020 |
| VLSI43 |
The Mesochronous Dual-Clock FIFO Buffer |
Area / Delay |
VHDL/2020 |
| VLSI44 |
DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy |
Area / Delay |
VHDL/2020 |
| VLSI45 |
Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays |
Area / Delay |
VHDL/2020 |
| VLSI46 |
Low-Complexity Distributed-Arithmetic-Based Pipelined Architecture for an LSTM Network |
Area / Delay |
VHDL/2020 |
| VLSI47 |
Algorithm and Architecture of an Efficient MIMO Detector With Cross-Level Parallel Tree-Search |
Area / Delay |
VHDL/2020 |
| VLSI48 |
Conflux—An Asynchronous Two-to-One Multiplexor for Time-Division Multiplexing and Clockless, Tokenless Readout |
Area / Delay |
VHDL/2020 |
| VLSI49 |
Slicing FIFOs for on-chip memory bandwidth exhaustion |
Area / Delay |
VHDL/2020 |
| VLSI50 |
Res-DNN: A Residue Number System-Based DNN Accelerator Unit |
Area / Delay |
VHDL/2020 |
| VLSI51 |
Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs |
Area / Delay |
VHDL/2020 |
| VLSI52 |
Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage Scaling |
Area / Delay |
VHDL/2020 |
| VLSI53 |
POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator |
Area / Delay |
VHDL/2020 |
| VLSI54 |
N -Dimensional Approximation of Euclidean Distance |
Area / Delay |
VHDL/2020 |
| VLSI55 |
A Stochastic Computing Architecture for Iterative Estimation |
Area / Delay |
VHDL/2020 |
| VLSI56 |
FPGA-Based True Random Number Generation Using Programmable Delays in Oscillator-Rings |
Area / Delay |
VHDL/2020 |
| VLSI57 |
Runtime Efficiency-Accuracy Tradeoff Using Configurable Floating Point Multiplier |
Area / Delay |
VHDL/2020 |
| VLSI58 |
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs |
Area / Delay |
VHDL/2020 |
| VLSI59 |
Optimal Runtime Algorithm to Improve Fault Tolerance of Bus-Based Reconfigurable Designs |
Area / Delay |
VHDL/2020 |
| VLSI60 |
GH CORDIC-Based Architecture for Computing N th Root of Single-Precision Floating-Point Number |
Area / Delay |
VHDL/2020 |
| VLSI61 |
Design Exploration of Energy-Efficient Accuracy-Configurable Dadda Multipliers With Improved Lifetime Based on Voltage Overscaling |
Area / Delay |
VHDL/2020 |
| VLSI62 |
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation |
Area / Delay |
VHDL/2020 |
| VLSI63 |
Design of Approximate Booth Squarer for Error-Tolerant Computing |
Area / Delay |
VHDL/2020 |
| VLSI64 |
Parallel architecture of power-of-two multipliers for FPGAs |
Area / Delay |
VHDL/2020 |
| VLSI65 |
Low-Latency Reconfigurable Entropy Digital True Random Number Generator With Bias Detection and Correction |
Area / Delay |
VHDL/2020 |
| VLSI66 |
Stochastic Mixed-PR: A Stochastically-Tunable Low-Error Adder |
Area / Delay |
VHDL/2020 |
| VLSI67 |
Area–delay and energy efficient multi-operand binary tree adder |
Area / Delay |
VHDL/2020 |
| VLSI68 |
Block-Based Carry Speculative Approximate Adder for Energy-Efficient Applications |
Area / Delay |
VHDL/2020 |
| VLSI69 |
Optimizing FPGA Logic Block Architectures for Arithmetic |
Area / Delay |
VHDL/2020 |
| VLSI70 |
RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs |
Area / Delay |
VHDL/2020 |
| VLSI71 |
Fast Hybrid Karatsuba Multiplier for Type II Pentanomials |
Area / Delay |
VHDL/2020 |
| VLSI72 |
Design Approach for Ring Amplifiers |
Area / Delay |
VHDL/2020 |
| VLSI73 |
Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers |
Area / Delay |
VHDL/2020 |
| VLSI74 |
Design and Implementation of a Low-Latency Modular Multiplication Algorithm |
Area / Delay |
VHDL/2020 |
| VLSI75 |
A Highly Efficient Conditional Feedthrough Pulsed Flip-Flop for High-Speed Applications |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI76 |
ASP-SIFT: Using Analog Signal Processing Architecture to Accelerate Keypoint Detection of SIFT Algorithm |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI77 |
A Novel Time-Shared and LUT-Less Pipelined Architecture for LMS Adaptive Filter |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI78 |
An FPGA-Based 1-GHz, 128 × 128 Cross-Correlator for Aperture Synthesis Imaging |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI79 |
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI80 |
A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI81 |
A 2.56-Gb/s Serial Wireline Transceiver That Supports an Auxiliary Channel in 65-nm CMOS |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI82 |
Design and Implementation of Encryption/Decryption Architectures for BFV Homomorphic Encryption Scheme |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI83 |
High-Resolution All-Digital Transmit Beamformer for High-Frequency and Wearable Ultrasound Imaging Systems |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI84 |
A Compact Fully Passive Loop Filter-Based Continuous Time Modulator for Multi-Channel Biomedical Applications |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI85 |
Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault Attacks |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI86 |
Jitter Minimization in Digital PLLs with Mid-Rise TDCs |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI87 |
A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI88 |
RLWE-Oriented High-Speed Polynomial Multiplier Utilizing Multi-Lane Stockham NTT Algorithm |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI89 |
DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI90 |
Approximate memory compression for energy-efficiency |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI91 |
A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI92 |
A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI93 |
Analysis and Design of Unified Architectures for Zero-Attraction-Based Sparse Adaptive Filters |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI94 |
High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI95 |
High Throughput Spatial Convolution Filters on FPGAs |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI96 |
A 0.6-V Power-Efficient Active-RC Analog Low-Pass Filter With Cutoff Frequency Selection |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI97 |
An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI98 |
Low Flicker Dimmable Multichannel LED Driver With Matrix-Style DPWM and Precise Current Matching |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI99 |
A 0.6-V Power-Efficient Active-RC Analog Low-Pass Filter With Cutoff Frequency Selection |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI100 |
Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI101 |
Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI102 |
Design Method for RF Energy Harvesting Rectifiers |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI103 |
Sparse FIR filter design via partial L1 optimization |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI104 |
Fractional-N PLL With Hybrid IIR Noise Filtering |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI105 |
Reconfigurable Digital Delta-Sigma Modulation Transmitter Architecture for Concurrent Multi-Band Transmission |
HIGH SPEED TRANSMISSION |
VHDL/2020 |
| VLSI106 |
A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement |
AUDIO / IMAGE & VIDEO Processing |
VHDL/2020 |
| VLSI107 |
A Modified Inexact Arithmetic Median Filter for Removing Salt-and-Pepper Noise From Gray-Level Images |
AUDIO / IMAGE & VIDEO Processing |
VHDL/2020 |
| VLSI108 |
FPGA-Based Implementation of a Real-Time Object Recognition System Using Convolutional Neural Network |
AUDIO / IMAGE & VIDEO Processing |
VHDL/2020 |
