| VLSI1 |
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration |
Low power |
2019 |
| VLSI2 |
Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow Phase-Noise Cellular Applications |
Low power |
2019 |
| VLSI3 |
Multi loop Control for Fast Transient DC–DC Converter |
Low power |
2019 |
| VLSI4 |
Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation |
Low power |
2019 |
| VLSI5 |
A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC |
Low power |
2019 |
| VLSI6 |
Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs |
Low power |
2019 |
| VLSI7 |
A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS |
Low power |
2019 |
| VLSI8 |
Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate |
Low power |
2019 |
| VLSI9 |
Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction |
Low power |
2019 |
| VLSI10 |
Radiation-Hardened 14T SRAM Bit cell With Speed and Power Optimized for Space Application |
Low power |
2019 |
| VLSI11 |
A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs |
Low power |
2019 |
| VLSI12 |
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors |
Low power |
2019 |
| VLSI13 |
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS |
Low power |
2019 |
| VLSI14 |
A Wideband Low-Noise Variable-Gain Amplifier with a 3.4 dB NF and up to 45 dB gain tuning range in 130 nm CMOS |
Low power |
2019 |
| VLSI15 |
A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control |
High speed and signal processing |
2019 |
| VLSI16 |
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175 μW/Channel in 65-nm CMOS |
High speed and signal processing |
2019 |
| VLSI17 |
Feed forward-Cut set-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator |
High speed and signal processing |
2019 |
| VLSI18 |
An Analog LO Harmonic Suppression Technique for SDR Receivers |
High speed and signal processing |
2019 |
| VLSI19 |
CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency |
High speed and signal processing |
2019 |
| VLSI20 |
Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI |
High speed and signal processing |
2019 |
| VLSI21 |
Design of Reconfigurable Digital IF Filter with Low Complexity |
High speed and signal processing |
2019 |
| VLSI22 |
Multiplier-free Implementation of Galois Field Fourier Transform on a FPGA |
High speed and signal processing |
2019 |
| VLSI23 |
Analysis and Optimization of Multi section Capacitive DACs for Mixed-Signal Processing |
High speed and signal processing |
2019 |
| VLSI24 |
A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G |
High speed and signal processing |
2019 |
| VLSI25 |
A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient |
High speed and signal processing |
2019 |
| VLSI26 |
An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops |
High speed and signal processing |
2019 |
| VLSI27 |
Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping |
High speed and signal processing |
2019 |
| VLSI28 |
Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data |
High speed and signal processing |
2019 |
| VLSI29 |
A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace |
Area efficient/ timing & VHdelay reduction |
2019 |
| VLSI30 |
Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications |
Area efficient/ timing & delay reduction |
2019 |
| VLSI31 |
A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories |
Area efficient/ timing & delay reduction |
2019 |
| VLSI32 |
Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data |
Area efficient/ timing & delay reduction |
2019 |
| VLSI33 |
Rapid Balise Telegram Decoder with Modified LFSR Architecture for Train Protection Systems |
Area efficient/ timing & delay reduction |
2019 |
| VLSI34 |
Area-Time Efficient Streaming Architecture for FAST and BRIEF Detector |
Area efficient/ timing & delay reduction |
2019 |
| VLSI35 |
Efficient Design for Fixed-Width Adder-Tree |
Area efficient/ timing & delay reduction |
2019 |
| VLSI36 |
An Energy-efficient Accelerator based on Hybrid CPU-FPGA Devices for Password Recovery |
Area efficient/ timing & delay reduction |
2019 |
| VLSI37 |
Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA |
Area efficient/ timing & delay reduction |
2019 |
| VLSI38 |
A Combined Arithmetic-High-Level Synthesis Solution to Deploy Partial Carry-Save Radix-8 Booth Multipliers in Data paths |
Area efficient/ timing & delay reduction |
2019 |
| VLSI39 |
Hardware-Efficient Post-processing Architectures for True Random Number Generators |
Area efficient/ timing & delay reduction |
2019 |
| VLSI40 |
New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata |
Area efficient/ timing & delay reduction |
2019 |
| VLSI41 |
A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS |
Low power |
2019 |
| VLSI42 |
A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC |
Low power |
2019 |
| VLSI43 |
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-μm CMOS Utilizing Pulse-Shrinking Fine Stage With Built- In Coarse Gain Calibration |
Low power |
2019 |
| VLSI44 |
A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs |
Low power |
2019 |
| VLSI45 |
A Wideband Low-Noise Variable-Gain Amplifier with a 3.4 dB NF and up to 45 dB gain tuning range in 130 nm CMOS |
Low power |
2019 |
| VLSI46 |
Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate |
Low power |
2019 |
| VLSI47 |
Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction |
Low power |
2019 |
| VLSI48 |
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors |
Low power |
2019 |
| VLSI49 |
Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation |
Low power |
2019 |
| VLSI50 |
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS |
Low power |
2019 |
| VLSI51 |
Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications |
Low power |
2019 |
| VLSI52 |
Multiloop Control for Fast Transient DC–DC Converter |
Low power |
2019 |
| VLSI53 |
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application |
High speed and signal processing |
2019 |
| VLSI54 |
A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient |
High speed and signal processing |
2019 |
| VLSI55 |
A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G |
High speed and signal processing |
2019 |
| VLSI56 |
An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops |
High speed and signal processing |
2019 |
| VLSI57 |
An Analog LO Harmonic Suppression Technique for SDR Receivers |
High speed and signal processing |
2019 |
| VLSI58 |
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175 μW/Channel in 65-nm CMOS |
High speed and signal processing |
2019 |
| VLSI59 |
Analysis and Optimization of Multisection Capacitive DACs for Mixed-Signal Processing |
High speed and signal processing |
2019 |
| VLSI60 |
CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency |
High speed and signal processing |
2019 |
| VLSI61 |
Design of Reconfigurable Digital IF Filter with Low Complexity |
High speed and signal processing |
2019 |
| VLSI62 |
Feedforward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator |
High speed and signal processing |
2019 |
| VLSI63 |
Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping |
High speed and signal processing |
2019 |
| VLSI64 |
Multiplier-free Implementation of Galois Field Fourier Transform on a FPGA |
High speed and signal processing |
2019 |
